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| AT16244 Features * * * * * * * Fastest Propagation Speeds in the Industry TPD (F grade) = 2.5 ns, TPD (G grade) = 2.0 ns Maximum derating for capacitive loads 1.5ns/100 pF (F grade) and 1.1 ns/100 pF (G grade) Very low ground bounce < 0.6V @ VCC =5.00 V, Ta=25C Excellent noise rejection Typical output skew 0.25ns TM Bus Hold circuitry to retain last active state during Tri-StateTM Available in SSOP and TSSOP packages Description Atmel's Fast Logic 16-Bit Buffer/Line driver provides bus interface and signal buffering at the fastest speeds available in the industry. The Tri-state outputs can be set for either 4-bit, 8-bit, or 16-bit independent operation. The AT16244 also has bus-hold circuitry which retains the last state of the input whenever a high impedance level is detected, and eliminates the need for pull-up or pull-down resistors. Minimal ground bounce and high input noise rejection make this device excellent for use in all high speed interface applications. AT16244 Fast LogicTM 16-Bit Buffer/Line Driver AT16244F AT16244G Functional Block Diagram (1) Note: 1. The function shown is repeated 3 additional times on each device. SSOP/TSSOP 1OE 1Y1 GND 1Y4 2Y1 GND 2Y4 3Y2 3Y3 VCC 4Y2 4Y3 4OE 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 48 46 44 42 40 38 36 34 32 30 28 26 47 45 43 41 39 37 35 33 31 29 27 25 1A1 GND 1A4 2A1 GND 2A4 3A2 3A3 VCC 4A2 4A3 3OE 2OE 1A2 1A3 VCC 2A2 2A3 3A1 GND 3A4 4A1 GND 4A4 1Y2 1Y3 VCC 2Y2 2Y3 3Y1 GND 3Y4 4Y1 GND 4Y4 Pin Configurations Pin Names xOE xA xY Descriptions Output Enable Input (Active Low) Data Inputs Tri-State Outputs Top View 0755B 5-3 Function Table(1) Inputs xOE L L H Note: 1. X = Don't Care, Z = High Impedance *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: 1. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC +0.75V dc which may overshoot to +7.0V for pulses of less than 20 ns. Outputs xA L H X xY L H Z Absolute Maximum Ratings* Operating Temperature ........................ 0C to +70C Storage Temperature ...................... -65C to +150C Voltage on any Pin with Respect to Ground...................-2.0V to +7.0V(1) Maximum Operating Voltage.............................. 6.0V 5.0 Volt DC Characteristics Symbol ICC VIH VIL IIH IIL IOZ VOH(1) VOH(2) V OL V OL Note: Applicable over recommended operating range from Ta = 0C to +70C, VCC = +5.0V +/- 5% (unless otherwise noted) Parameter Quiescent Power Supply Current Input High Voltage Input Low Voltage Input High Current (I/O Pins) Input Low Current (I/O Pins) Output Leakage Current Output High Voltage F Grade only Output High Voltage G Grade only Output Low Voltage (F Grade) Output Low Voltage (G Grade) VCC = 4.75V IOH = -10 mA VCC = 4.75V IOH = -12 mA IOL = 10 mA IOL = 12 mA 2.7 2.7 0.55 0.55 VIN = VCC VIN = GND Test Conditions VCC = Max, VIN = 3.4V 2.0 0.8 15 15 10 Min Typ 0.8 Max 1.2 Units mA V V A A mA V V V V 1. F grade: At VCC (max), the value of VOH(max) = 3.75V and at VCC(min), VOH(max) = 3.25V 2. G grade: At VCC (max), the value of VOH(max) = 3.75V and at VCC(min), VOH(max) = 3.35V 5-4 AT16244 AT16244 AC Characteristics AT16244F Applicable over recommended operating range from Ta = 0C to +70C, VCC = 5.0V +/- 5% (unless otherwise noted) Symbol tPHL tPLH tPZH tPZL tPHZ tPLZ tSK(1) tPHL(1) tPLH Note: Parameter Propagation Delay Output Enable Time Output Disable Time Output Skew Propagation Delay vs Output Loading Test Conditions CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max 2.5 5.5 6.0 0.5 Units ns ns ns ns ns/100 pF 1.3 1.5 1. This parameter is guaranteed but not 100% tested. AT16244G Applicable over recommended operating range from Ta = 0C to +70C, VCC = 5.0V +/- 5% (unless otherwise noted) Symbol tPHL tPLH tPZH tPZL tPHZ tPLZ tSK(1) tPHL(1) tPLH Note: Parameter Propagation Delay Output Enable Time Output Disable Time Output Skew Propagation Delay vs Output Loading Test Conditions CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max 2.0 5.5 5.0 0.5 Units ns ns ns ns ns/100 pF 0.9 1.1 1. This parameter is guaranteed but not 100% tested. Test Circuits(1,2) VCC 7.0V Switch Position Test Open Drain Disable Low Enable Low All Other Tests 50 pF Switch Closed Open 500 VIN Pulse Generator RT D.U.T. VOUT 500 CL Definitions: CL= Load capacitance; Includes jig and probe capacitance. RT=Termination resistance; Should be equal to ZOUT of the Pulse Generator. Note: 1. Pulse Generator: Rate 1.0 MHz, tF 2.5 ns, tR 2.5 ns. 2. AC tests are done with a single bit switching, and timings need to be derated when multiple outputs are switching in the same direction simultaneously. This derating should not exceed 0.5 ns for 16 inputs switching simultaneously. 5-5 IOL Pull Down Current 160 120 IOL, mA 80 40 0 -40 Time 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 IOL Output, V Output, V Ground Bounce for High to Low Transitions(1) 3.5 3.0 2.5 2.0 gnd - measured on output with input held constant output Supply Bounce for Low to High Transitions(2) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 Time VOHV VOHP vcc measured on output with input held constant output Volts 1.5 1.0 0.5 0.0 VOLV VOLP -0.5 Time Typical Values Parameter VOLP VOLV VOHV VOHP Note: Value 0.4 -0.26 VCC - 0.13 VCC + 0.6 Volts Units V V V V 1. When multiple outputs are switched at the same time, rapidly changing current on the ground and VCC paths causes a voltage to develop across the parasitic inductance of the wire bond and package pins. This occurrence is called simultaneous switching noise. Atmel's AT16244 products have minimized this phenomenon as shown on the graph. Output data is for 15 outputs switching simultaneously at a frequency of 1 MHz. The ground data is measured on the one remaining output, which is set to logic low and will reflect any device ground movement. 2. As on the graph for Ground Bounce, a similar condition occurs for low to high transitions. Output data is for 15 outputs switching simultaneously at a frequency of 1 MHz. VCC droop is measured on the one remaining output pin, which is set to a logic high. This output will reflect any movement on the device VCC. 5-6 AT16244 AT16244 Propagation Delay Waveforms Input Transition 1.5 V tPLH 1.5 V tPHL VOH Output Transition 1.5 V VOL Enable and Disable Waveforms Enable Disable 3.0 V 1.5 V 0V tPZL tPLZ 3.5 V Switch Closed 1.5 V 0.3 V tPZH tPHZ 0.3 V 1.5 V Switch Open 0V VOH VOL Control Input Output Switched Low Output Switched High 5-7 Ordering Information TPD 2.5 ns 2.0 ns Ordering Code AT16244F - 25YC AT16244F - 25XC AT16244G - 20YC AT16244G - 20XC Package 48Y 48X 48Y 48X Operation Range Commercial Commercial Package Type 48X 48Y 48 Pin, Plastic Thin Shrink Small Outline Package (TSSOP) 48 Pin, Plastic Shrink Small Outline Package (SSOP) 5-8 AT16244 |
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